1. Technical Field
This invention relates generally to the manufacture of semiconductor integrated circuits, and more specifically to a dry etch process for use with devices having a silicon nitride (SiN) etch stop layer. The process yields a high etch rate selectivity of oxide to nitride (i.e., the ratio of the etch rate of the oxide to the etch rate of the SiN) and thereby provides an advantage in the fabrication of borderless contact structures. The chemical etching process is carried out in a reactive ion etch reactor, utilizing a gaseous etchant mixture comprising a carbon-fluoride gas having the formula C.sub.4 F.sub.8, an inert gas, preferably Ar and optionally, carbon oxide gas, CO.
2. Background Art
The cell size of dynamic random access memories (DRAMs) can be decreased by as much as 40% by using bitline contacts that are borderless to wordlines. A feature integral to the formation of borderless contacts is the use of etch stop layers, an example of which is silicon nitride,Si.sub.3 N.sub.4 (SiN).
The SiN etch stop process is the most promising method for forming borderless contacts on devices with dimensions below 0.5 .mu.m. Due to these narrow contact dimensions, a very thin SiN etch stop layer is used in order to maximize contact area and minimize contact resistance. Therefore, a very high etch rate selectivity between oxides, such as phospho-silicate glass and SiN is required for the fabrication of integrated circuits that use SiN etch stop layers.
High oxide to SiN etch rate selectivity has previously been obtained using process chemistries such as C.sub.2 F.sub.6 and C.sub.3 F.sub.8. These processes have been performed on unique, and/or one-of-a-kind process tools which have not found wide acceptance in the microelectronics manufacturing industry. In addition, the ability to selectively etch oxide over nitride when the underlying SiN topography was not flat, i.e., has greater than one depth, has been a technologic roadblock.
It is known in the prior art that the manufacture of multilayer structures typically involves patterned etching of areas of the semiconductor surface which are covered by a photoresist protective material. One well known etching technique is reactive ion etching (RIE). This process involves positioning a semiconductor wafer in a reaction chamber and feeding etchant gases into the chamber. The etchant gases are dissociated in an RF field so that ions contained in the etchant gases are accelerated to the wafer surface. The accelerated ions combine chemically with unmasked material on the wafer surface. As a result, volatile etch product is produced and is incorporated into the plasma. The concentration of the volatile etch product can be tracked in order to determine the end-point of the RIE process, i.e., when the chemical reaction has removed the desired level of material from the wafer surface. During the RIE process, a single layer or multiple layers of material or film may be removed. These materials may include, for example, SiN, PSG, silicon dioxide (SiO.sub.2) and poly-silicon (PSi).
U.S. Pat. No. 5,266,154, issued Nov. 30, 1993 to Tatsumi, discloses a dry etch method which can be applied to contact hole formation in which octafluorocyclobutane is used as the etching gas to etch an SiO.sub.2 inter-layer insulation film.
U.S. Pat. No. 5,286,344, issued Feb. 15, 1994 to Blalock et al., discloses a process for selectively etching a layer of SiO.sub.2 on an underlying stop layer of SiN. This process utilizes a fluorinated chemical etchant system, comprising an etchant material and an additive material. The additive material comprises a fluorocarbon material in which the number of hydrogen atoms is equal to or greater than the number of fluorine atoms. Preferably, the additive material is CH.sub.2 F.sub.2. The etchant material comprises at least one of CHF.sub.3, CF.sub.4 or Ar.
U.S. Pat. No. 5,173,151, issued Dec. 22, 1992 to Namose, discloses a dry chemical etching method for etching one or more deposited Si or SiO.sub.2 layers, utilizing an etching medium comprised of C.sub.n F.sub.2n+2, wherein n is an integer, and an inert gas, such as He or Ar.
U.S. Pat. No. 5,176,790 issued Jan. 5, 1993 to Arleo et al., teaches a process for etching through an insulation layer over a metal layer, without an etch stop layer, on a semiconductor wafer which comprises plasma etching the insulation layer with a fluorine-containing gaseous etchant mixture. The mixture will include one or more 3-6 carbon fluorinated hydrocarbon gases either alone or in combination with one or more nitrogen-containing gases.
U.S. Pat. No. 5,302,236, issued on Apr. 12, 1994 to Tahara et al., discloses a method of etching an oxide or nitride film with a gaseous etchant mixture of a fluorine-containing gas and a sufficiently greater volume of carbon monoxide gas.
None of the prior art teaches a dry etch process for creating borderless contacts in small dimensional structures utilizing silicon nitride etch stop layers. Previous process chemistries, such as C.sub.2 F.sub.6 and C.sub.3 F.sub.8, which have been utilized to provide high oxide-nitride etch rate selectivity have found application only with unique, or one-of-a-kind process tools.
Therefore, there existed a need to provide a process for use in fabricating small sized structures utilizing silicon nitride etch stop liners, which results in a high etch selectivity between oxide and the nitride liner.